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GPIB 72010

DISCONTINUED.  GPIB 72010: NEC72010C, TMS9914A Compatible

Currently being redeveloped as iGPIB-72110, and  iGPIB-72120

Search for "iGPIB-721": at for current information.

Main Features

  • CMOS replacements for original NEC 7210C or TMS 9914A NMOS devices. Works with any application software written for these chips.
  • SMD mounting.
  • Single chip solution for GPIB interfaces.
  • Full synchronous chip design ensures proper chip timing for highest reliability.
  • Integrated GPIB line drivers obsolete the use of the discrete 75161 or 75162 type line drivers, which will make the iGPIB series the most cost-effective solution for existing and new GPIB designs.
  • Starts up in NEC 7210C compatible mode, switch to M4882 and TMS 9914A mode by software.
  • Enhancements in M4882 mode:
    • Timeout counter
    • Transfer counter
    • Bus line monitor
    • Extended EOS handling
    • Synchronous DMA with 30MByte/s bandwidth saving CPU time.
  • Any iGPIB can utilize enhanced features of the extended M4882 mode by software


This chip series contains the knowledge of more than 12 years of experience in GPIB bus technology. The chips have been used in ines GPIB ISA, PCMCIA, PCI and CompactPCI cards for over 5 years.


iGPIB 72010

NEC 7210C

TMS 9914A

Synchronous chip design Yes No No
FIFO 2 x 255 byte No No
Hardware Timeout Counter 16bit No No
Handling of up to 3 EOS byte Yes No No
SN75161 / 75162 line drivers included  Yes No No
Bus line monitor Yes No No
Hardware Transfer Counter Yes No No
Single chip solution Yes No No
Manufacturing Process CMOS NMOS NMOS
Available Packages  QFP80  DIL40 PLCC44


ines offers a family of reliable, enhanced, high-performance and backward-compatible CMOS GPIB interface ICs, called the iGPIB series. Though available in a variety of packages, all devices contain the same silicon chip design. Any device can operate as GPIB controller as well as GPIB device (Talker/Listener only).

The iGPIB 72010 chip can be used for:

  • Replacement of NEC 7210C designs: The synchronous chip design ensures stable timing, better than in the original chip that uses asynchronous design. After reset, the chip behaves exactly as 7210. The QFP package can be used to create circuit boards using SMD technology while retaining existing software.
  • Replacement of TMS 9914A designs: The iGPIB chip works too in TMS 9914A mode. The mode can be selected by software.
  • New designs: They take advantage of the enhanced iGPIB chip features in the enhanced mode called M4882, for example, the integrated FIFO buffers. DMA circuitry is no longer necessary, nevertheless available, for obtaining high speeds, in contrast to existing designs. The built-in support for IEEE 488.2 compliant functions ease the instruments system design. The integrating timeout and transfer counters make software simulated counters obsolete. These features keep costs down and simplifies hardware and software development significantly.

Block Diagram

Enhanced features in M4882 mode

Data Transfer The data transfer to or from the GPIB is performed via two 255 Byte wide FIFO registers/buffers. These FIFOs are used to decouple GPIB data traffic from the CPU bus. Using the iGPIB as an IEEE 488.2 device, the FIFOs may be used as the input or output queue what simplifies the software design significantly. In addition, provisions were made to support the IEEE 488.2 Trigger Control and to support the MAV (Message Available) Reset directly in the hardware.
The last feature is unique by ines. The FIFOs may be accessed respectively with simple "read" and "write" operations (to the DIR or CDOR). Using this technique combined with repetitive move instructions (i.e. REP INSB of the 80386 CPU) allows to use the full band width without using DMA.
Bus Line Control
and Monitoring
The iGPIB independently controls and monitors each bus line as well as the transceiver control signals. This feature exceeds the IEEE 488.2 requirements (monitoring NRFD and NDAC).
Timeout counter The iGPIB provides a timeout interrupt condition. If the condition is unmasked, a timer counts down for a programmable interval. Any time a data transmission takes place, the timer will be reset to its original (programmed) value. If the handshake gets stuck, the timer underflows and an interrupt occurs. The timeout is from 1 ms up to 65 s in steps of 1 ms. Normally the timeout functionality had to be provided by the interface driver software, which is not necessary anymore now.
Transfer Counter The iGPIB offers a 16-bit wide transfer counter. This counter reduces the programming for DMA operations in two ways. First, the counter delivers an end-of-transfer interrupt, if a programmable amount of data has been sent or received, respectively. The driver software can initiate a DMA transfer and then switch to another task until the interrupt occurs. Second, a Last Byte Handling feature allows to automatically send the last byte with EOI true. This means, on send transfers (talker), it indicates the end of a data block. On receive transfers, it is possible to automatically signal NRFD active after the last byte has been received (listener). With previous GPIB controllers, like the NEC 7210C, all these operations had to be programmed explicitly via software.
IEEE 488.2
Service Request
In order to integrate the preferred IEEE 488.2 implementation of requesting service, the iGPIB realizes the Service-Request-Enable register on chip. This allows to update the status byte via the status byte register independent of requesting service. Together with two transition filters for each status bit, the iGPIB handles the service request generation autonomously without any software intervention. Further, the MAV bit of the IEEE 488.2 status byte can be reset automatically, if a message (data block) has been sent. This solves the problem of differing speeds between device and controller, which has not been specified sufficiently in the IEEE 488.2 standard.
The IEEE 488.2 standard explicitly recommends more than one stop-handshake condition for an IEEE 488.2 Controller. Previous Controllers allow only to use EOI and one EOS byte. The iGPIB instead allows to use EOI and up to three EOS bytes. The iGPIB entirely meets the IEEE 488.2 standard recommendations in hardware, at the same time reducing the software overhead. In addition, the Controller allows to ignore EOI as a stop-handshake condition. This simplifies the handling of pre-488.2 devices and devices not entirely operating according to the standard.
DMA Interface
The iGPIB FIFOs may be accessed via the synchronous DMA interface (XDMA). This interface enables FIFO access without using the CPU data bus. XDMA can transfer data at a speed of up to 30 MByte/s. This interface may be used for various purposes. High speed / high perfomance instruments, for example, may transfer data directly to the GPIB FIFO without any CPU intervention. Computers acting as GPIB controllers can perform DMA cycles utilizing the full band width of their busses, i.e. even with 64-bit architectures, up to 128 bit busses.

QFP80 Pinout


For instrument manufacturers ines decided to ease the upgrading of the IEEE 488.1 to 488.2 standard definitions with SCPI by offering the "ines-ieee488.2" device driver software in a package together with the developer kit of the chip.
  • The license for the driver is free of charge and provides the user with the latest features of the IEEE 488.2.
  • This software provides routines to the iGPIB chip in IEEE 488.2 devices. It may also be used for systems which do not use the IEEE 488.2 protocol, but require a GPIB stream-like interface.
  • The software is written in ANSI compatible C and may be compiled for any microprocessor.
  • The iGPIB developer kit includes the "ines-ieee488.2" device driver software (for instruments only). This software may be adapted to any hardware platform easily.
  • For demonstration reasons Ines provides a demo package for PC's. The demo shows how to use the device driver software and reduces any programming effort for the engineer.
  • All iGPIB designs support the requirements and optional recommendations of the IEEE 488.2 standard and are backwards compatible to existing NEC 7210C applications.
  • Instrument manufacturers presently using the NEC 7210C can easily upgrade IEEE 488.1 instruments by simply replacing it with this iGPIB chip.
  • All iGPIBs are equipped with the two 255 byte FIFOs.


Ordering Information

GPIB-C-72010 GPIB 72010 Controller Chip DISCONTINUED  Search for "iGPIB-721": at for current information.


GPIB 72010 Device Chip

DISCONTINUED  Search for "iGPIB-721": at for current information.


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